1. Modulus refers to ____________
a) A method used to fabricate decade counter units
b) The modulus of elasticity, or the ability of a circuit to be stretched from one mode to another
c) An input on a counter that is used to set the counter state, such as UP/DOWN
d) The maximum number of states in a counter sequence
View Answer
Answer: d
Explanation: Modulus is defined as the maximum number of stages/states a counter has. It is
independent of the number of states the counter will actually traverse.
2. A sequential circuit design is used to ____________
a) Count up
b) Count down
c) Decode an end count
d) Count in a random order
View Answer
Answer: d
Explanation: A sequential circuit design is used to count in a random manner which is faster than the
combinational circuit. It is used for storing data.
3. In general, when using a scope to troubleshoot digital systems, the instrument should be triggered
by ____________
a) The A channel or channel 1
b) The vertical input mode, when using more than one channel
c) The system clock
d) Line sync, in order to observe troublesome power line glitches
View Answer
Answer: c
Explanation: All the information is sent from one end to another end through the clock pulse which
behaves like a carrier. So, for troubleshooting it should be triggered by the same. Since the system
clock is internally produced.
4. Which counters are often used whenever pulses are to be counted and the results displayed in
decimal?
a) Synchronous
b) Bean
c) Decade
d) BCD
View Answer
Answer: d
Explanation: BCD means Binary Coded Decimal, which means that decimal numbers coded of binary
numbers. It displays the decimal equivalent of corresponding binary numbers.
5. The ________ counter in the Altera library has controls that allow it to count up or down, and
perform synchronous parallel load and asynchronous cascading.
a) 74134
b) LPM
c) Synchronous
d) AHDL
View Answer
Answer: b
Explanation: The library of parameterized modules (LPM) counter in the Altera library has controls
that allow it to count up or down, and perform synchronous parallel load and asynchronous
cascading.
6. The minimum number of flip-flops that can be used to construct a modulus-5 counter is
____________
20a) 3
b) 8
c) 5
d) 10
View Answer
Answer: a
Explanation: The minimum number of flip-flops used in a counter is given by: 2(n-1)<=N<=2n.
Thus, for modulus-5 counter: 22 <= N <= 23, where N = 5 and n = 3.
7. The duty cycle of the most significant bit from a 4-bit (0–9) BCD counter is ____________
a) 20%
b) 50%
c) 10%
d) 80%
View Answer
Answer: a
Explanation: There are 10 states, out of which MSB is high only for (1000, 1001) 2 times. Hence duty
cycle is 2/10*100 = 20%. Since the duty cycle is the ratio of on-time to the total time.
8. Normally, the synchronous counter is designed using ____________
a) S-R flip-flops
b) J-K flip-flops
c) D flip-flops
d) T flip-flops
View Answer
Answer: b
Explanation: Since J-K flip-flops have options of recovery from toggle condition and by using less
number of J-K flip-flops a synchronous counter can be designed. So, it is more preferred. Also,
because JK-flip-flops resolves the problem of Forbidden States.
9. MOD-16 counter requires ________ no. of states.
a) 8
b) 4
c) 16
d) 32
View Answer
Answer: c
Explanation: 2n >= N >= 2(n-1), by using this formula we get the value of N=16 for n=4.
10. What is state diagram?
a) It provides the graphical representation of states
b) It provides exactly the same information as the state table
c) It is same as the truth table
d) It is similar to the characteristic equation
View Answer
Answer: b
Explanation: The state diagram provides exactly the same information as the state table and is
obtained directly from the state table.
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11. High speed counter is ____________
a) Ring counter
b) Ripple counter
c) Synchronous counter
d) Asynchronous counter
View Answer
Answer: c
Explanation: Synchronous counter doesn’t have propagation delay. Propagation delay refers to the
amount of time taken in producing the output when the input is altered.
12. Program counter in a digital computer ____________
a) Counts the number of programs run in the machine
b) Counts the number of times a subroutine
c) Counts the number of time the loops are executed
d) Points the memory address of the current or the next instruction
View Answer
Answer: d
Explanation: Program counter in a digital computer points the memory address of the current or the
next instruction which is to be executed.
13. Fundamental mode is another name for ____________
a) Level operation
b) Pulse operation
c) Clock operation
d) Edge operation
View Answer
Answer: b
Explanation: Whatever the input given to the devices are in the form of pulses always. That is why it
is known as a fundamental mode.
14. In an UP-counter, each flip-flop is triggered by ___________
a) The output of the next flip-flop
b) The normal output of the preceding flip-flop
c) The clock pulse of the previous flip-flop
d) The inverted output of the preceding flip-flop
View Answer
Answer: b
Explanation: In an UP-counter, each flip-flop is triggered by the normal output of the preceding
flip-flop. UP-counter counts from 0 to a maximum value.
15. In DOWN-counter, each flip-flop is triggered by ___________
a) The output of the next flip-flop
b) The normal output of the preceding flip-flop
c) The clock pulse of the previous flip-flop
d) The inverted output of the preceding flip-flop
View Answer
Answer: d
Explanation: In DOWN-counter, each flip-flop is triggered by the inverted output of the preceding
flip-flop. DOWN-counter counts from a maximum value to 0.
16. Binary counter that count incrementally and decrement is called ___________
a) Up-down counter
b) LSI counters
c) Down counter
d) Up counter
View Answer
Answer: a
Explanation: Binary counter that counts incrementally and decrement is called UP-DOWN
counter/multimode counter. It alternately counts up and down.
17. Once an up-/down-counter begins its count sequence, it ___________
a) Starts counting
b) Can be reversed
c) Can’t be reversed
d) Can be altered
View Answer
Answer: d
Explanation: In up/down ripple counter once the counting begins, we can simply change the pulse M
(mode control) M = 0 or 1 respectively for UP counter or Down counter.
18. In 4-bit up-down counter, how many flip-flops are required?
a) 2
b) 3
c) 4
d) 5
View Answer
Answer: c
Explanation: An n-bit bit counter requires n number of FFs. In a 4-bit up-down counter, there are 4
J-K flip-flops required.
19. A modulus-10 counter must have ________
a) 10 flip-flops
b) 4 Flip-flops
c) 2 flip-flops
d) Synchronous clocking
View Answer
Answer: b
Explanation: 2n-1 < = N < = 2n
For modulus-10 counter, N = 10. Therefore, 23 < = 10 < = 24. Thus, n = 4, and therefore, we require 4
FFs.
20. Which is not an example of a truncated modulus?
a) 8
b) 9
c) 11
d) 15
View Answer
Answer: a
Explanation: An n-bit counter whose modulus is less than the maximum possible is called a truncated
counter. Here, 9, 11 and 15 modulus counters are truncated counters. Whereas, modulus-8 is not a
truncated counter.
21. The designation means that the ________
a) Up count is active-HIGH, the down count is active-LOW
b) Up count is active-LOW, the down count is active-HIGH
c) Up and down counts are both active-LOW
d) Up and down counts are both active-HIGH
View Answer
Answer: a
Explanation: The designation means that the up count is active-HIGH, the down count is active-LOW.
Active-High means that up-count would be triggered when clock is 1 else when clock is 0,
down-count would be triggered, which is referred to as Active-low.
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22. An asynchronous binary up counter, made from a series of leading edge-triggered flip-flops, can
be changed to a down counter by ________
a) Taking the output on the other side of the flip-flops (instead of Q)
b) Clocking of each succeeding flip-flop from the other side (instead of Q)
c) Changing the flip-flops to trailing edge triggering
d) All of the Mentioned
View Answer
Answer: d
Explanation: By all of the mentioned ideas, an asynchronous binary up counter, made from a series
of leading edge-triggered flip-flops, can be changed to a down counter. Edge-triggered FFs refer to
FFs being triggered during a clock transition from LOW to HIGH or HIGH to LOW.
23. A 4-bit binary up counter has an input clock frequency of 20 kHz. The frequency of the most
significant bit is ________
a) 1.25 kHz
b) 2.50 kHz
c) 160 kHz
d) 320 kHz
View Answer
Answer: a
Explanation: Input clock is given by 20/2 kHz. So, count on the basis of 10 kHz clock. And MSB
changes on 8th stage; Hence, f = 10/8 = 1.25 kHz.
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