1. To realise one flip-flop using another flip-flop along with a combinational circuit, known as____________

a) PREVIOUS state decoder
b) NEXT state decoder
c) MIDDLE state decoder
d) PRESENT state decoder
View Answer
Answer: b
Explanation: To realise one flip-flop using another flip-flop along with a combinational circuit, known
as NEXT state decoder which acts as like a flip-flop.

2. For realisation of JK flip-flop from SR flip-flop, the input J and K will be given as ___________
a) External inputs to S and R
b) Internal inputs to S and R
c) External inputs to combinational circuit
d) Internal inputs to combinational circuit
View Answer
Answer: a
Explanation: If a JK Flip Flop is required, the inputs are given to the combinational circuit and the
output of the combinational circuit is connected to the inputs of the actual flip flop. So, J and K will
be given as external inputs to S and R. As SR flip-flop have invalid state and JK flip-flop don’t.

3. For realisation of JK flip-flop from SR flip-flop, if J=0 & K=0 then the input is ___________
a) S=0, R=0
b) S=0, R=X
c) S=X, R=0
d) S=X, R=X
View Answer
Answer: b
Explanation: If J=0 & K=0, the output will be as: Q(n)=0, Q(n+1)=0 and it is fed into both the AND
gates which results as S=0 & R=X(i.e. don’t care).
digital-circuits-questions-answers-entrance-exams-q3

4. For realisation of JK flip-flop from SR flip-flop, if J=1, K=0 & present state is 0(i.e. Q(n)=0) then
excitation input will be ___________
a) S=0, R=1
b) S=X, R=0
c) S=1, R=0
d) S=1, R=1
View Answer
Answer: c
Explanation: If J=1, K=0 & present state is 0(i.e. Q(n)=0) then next state will be 1 which results
excitation inputs as S=1 & R=0.
digital-circuits-questions-answers-entrance-exams-q3

5. For realisation of SR flip-flop from JK flip-flop, the excitation input will be obtained from
___________
a) S and R
b) R input
c) J and K input
d) D input
View Answer
Answer: c
Explanation: It is the reverse process of SR flip-flop to JK flip-flop. So, for realisation of SR flip-flop
from JK flip-flop, the excitation input will be obtained from J and K.

6. For realisation of SR flip-flop from JK flip-flop, if S=1, R=0 & present state is 0 then next state will
be ___________
a) 1
b) 0
c) Don’t care
d) Toggle
View Answer
Answer: a
Explanation: For JK flip-flop to SR flip-flop, if S=1, R=0 & present state is 0 then next state will be 1
because next stage is complement of present stage.
digital-circuits-questions-answers-entrance-exams-q6

7. For realisation of SR flip-flop from JK flip-flop, if S=1, R=0 & present state is 0 then the excitation
input will be ___________
a) J=1, K=1
b) J=X, K=1
c) J=1, K=X
d) J=0, K=0
View Answer
Answer: c
Explanation: For realisation of SR flip-flop from JK flip-flop, if S=1, R=0 & present state is 0 then the
excitation input will be J=1, K=X.
digital-circuits-questions-answers-entrance-exams-q6

8. The K-map simplification for realisation of SR flip-flop from JK flip-flop is ___________
a) J=1, K=0
b) J=R, K=S
c) J=S, K=R
d) J=0, K=1
View Answer
Answer: c
Explanation: The K-map simplification for realisation of SR flip-flop from JK flip-flop is given by: J=S,
K=R.

9. For realisation of D flip-flop from SR flip-flop, the external input is given through ___________
a) S
b) R
c) D
d) Both S and R
View Answer
Answer: c
Explanation: For realisation of D flip-flop from SR flip-flop, S and R are the actual inputs of the flip
flop which is connected together via NOT gate and it is called external input as D.

10. For D flip-flop to JK flip-flop, the characteristics equation is given by ___________
a) D=JQ(p)’+Q(p)K’
b) D=JQ(p)’+KQ(p)’
c) D=JQ(p)+Q(p)K’
d) D=J’Q(p)+Q(p)K
View Answer
Answer: a
Explanation: A characteristic equation is needed when a specific gate requires a specific output in
order to satisfy the truth table. For D flip-flop to JK flip-flop, the characteristics equation is given by
D=JQ(p)’+Q(p)K’

11.The output of a JK flipflop with asynchronous preset and clear inputs is ‘1’. The output can be
changed to ‘0’ with one of the following conditions
A. By applying J = 0, K = 0 and using a clock
B. By applying J = 1, K = 0 and using the clock
 C. By applying J = 1, K = 1 and using the clock
 D. By applying a synchronous preset input
 Answer: Option C
 Explanation:
 Preset state of JK Flip-Flop =1 With J=1 K=1 and the clock next state will be complement of
the present state

12. For which of the following purpose Karnaugh map is used
 A. Reducing the electronic circuits used
 B. To map the given Boolean logic function
 C. To minimize the terms in a Boolean expression
 D. To maximize the terms of a given a Boolean expression
Answer: Option C

13. How many two input AND and OR gates are required
 A. 2,2
 B. 2,3
 C. 3,3
 D. None of these
 Answer: Option A
 Explanation:
 Y=CD+EF+G
 Number of two input AND gates=2
 Number of two input OR gates = 2
 One OR gate to OR CD and EF and next to OR of G & output of first OR gate

14. For JK flip flop with J=1, K=0, the output after clock pulse will be ________
 A. 0
 B. 1
 C. High Impedance
 D. No change
Answer: Option B

15. To construct mod 30 counter __________ number of flip-flops are required
 A. 5
 B. 6
 C. 4
 D. 8
Answer: Option A
Explanation:
Mod - 30 counter +/- needs 5 Flip- Flop as 30 < 25
Mod - N counter counts total ' N ' number of states.
To count 'N' distinguished states we need minimum n Flip-Flop's as [N=2n]
For eg. Mod 16 counter requires 4 Flip- Flop's (16 = 24)

16. For which of the following two inputs, The NOR gate output will be low
 A. 01
 B. 10
 C. 11
 D. all the above
Answer: Option D
Explanation:
O/P is low if any one of the I/P is high

17. How many flip flops are required to construct a decade counter
 A. 10
 B. 3
 C. 4
 D. 2
Answer: Option C
Explanation:
Decade counter counts 10 states from 0 to 9 i.e (From 0000 to 1001) Thus 4 Flip-Flops are required

18. How many select lines will a 16 to 1 multiplexer will have
 A. 4
 B. 3
 C. 5
 D. 1
Answer: Option A
Explanation:
In 16 to 1 MUX four select lines will be required to select 16 (24)Inputs

19. To realize Y = CD+EF+G how many AND gates are required
 A. 4
 B. 5
 C. 3
 D. 2
Answer: Option D

20. To realize Y = CD + EF + G Two AND gates are required (for CD & EF).
The excess 3 code of decimal number 26 is
 A. 0100 1001
 B. 01011001
 C. 1000 1001
 D. 01001101
Answer: Option B
Explanation:
(26)10 in BCD is (00100110) BCD Add 011 to each BCD 01011001 for excess – 3

21. Which of the following gates are required to build a half adder
 A. EX-OR gate and NOR gate
 B. EX-OR gate and OR gate
 C. EX-OR gate and AND gate
 D. Four NAND gates.
Answer: Option C

22. Which of the following is the simplified Boolean algebra version of (x+y)(x+z)
 A. X
 B. x + x(y + z)
 C. x(1 + yz)
 D. x + yz
Answer: Option D
Explanation:
(x+y)(x+z) = xx+xz+yx+yz=x+xz+yx+yz
(since xx=x)
X(1+z)+xy+yz= x+ xy + yz (since 1+z=1)
X(1+y) + yz = x+yz (since 1+y =1)

23. If output of a logic gate is 1 when all its inputs are at logic 0. Then the gate is either
 A. a NAND or an EX-OR
 B. an OR or an EX-NOR
 C. an AND or an EX-OR
 D. a NOR or an EX-NOR
 Answer: Option D
 Explanation:

24.The asynchronous input can be used to set the flip-flop to the ____________
a) 1 state
b) 0 state
c) either 1 or 0 state
d) forbidden State
View Answer
Answer: c
Explanation: The asynchronous input can be used to set the flip-flop to the 1 state or clear the
flip-flop to the 0 state at any time, regardless of the condition at the other inputs.

25. Input clock of RS flip-flop is given to ____________
a) Input
b) Pulser
c) Output
d) Master slave flip-flop
View Answer
Answer: b
Explanation: Pulser behaves like an arithmetic operator, to perform the operation or determination
of corresponding states.

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